Product & Technology

A compiler for circuit boards.

Coppr takes engineering intent — written as a high-level spec or generated from a prompt — and compiles it through a structured intermediate representation into KiCad-compatible schematics, layouts, and Gerber files. Here's the full system, from the pipeline down to the agent that runs it.

The Pipeline

Intent in. Fab-ready output.

Intent

prompt / spec

Coppr IR

structured graph

Schematic

.kicad_sch

Layout

.kicad_pcb

Gerber

fab-ready

Architecture

The system, in one diagram.

Input

Prompt or Coppr spec. The agent parses intent into structured requirements.

Core

The Coppr IR — a typed graph of modules, components, nets, and constraints. Every agent action is a transaction on this graph.

Verification

ERC, DRC, DFM, SPICE, and BOM availability all wrap the compilation loop. Failures route back to the agent for revision.

Output

KiCad project files, Gerbers, drill files, pick-and-place, assembly BOM, and a full manufacturing-readiness report.

The Agent Harness

An LLM is not an engineer. This is.

A raw LLM hallucinates resistor values and forgets pin assignments. Coppr wraps the model in a harness of structured tools, retrieval, memory, and rules — the same way a junior EE is wrapped in textbooks, mentors, and design-review meetings.

A — RETRIEVAL

Datasheet RAG

Every component decision is grounded in the actual datasheet. Pin assignments, electrical limits, recommended layout patterns — extracted, indexed, and cited as evidence inline with the design.

B — MEMORY

Module Memory

Every verified module — USB-C power, LDO regulator, CAN transceiver — is stored as a parameterized recipe with roles, candidates, and checks. The library compounds with every board Coppr ships.

C — REASONING

Rule-Based Design

Deterministic rules — decoupling per IC, current-rated traces, manufacturer DFM profiles — run alongside the LLM. The model proposes; the rules verify. Both are required.

D — PLANNING

Tool Loop

The agent operates on the IR through typed tools: add_module(), select_component(), run_drc(), export_gerbers(). Every action is logged, reversible, and reviewable.

E — VERIFICATION

Closed-Loop Checks

ERC, DRC, DFM, SPICE, and BOM availability run continuously. Failures don't crash — they route back to the agent with structured error context and a fix prompt.

F — PROVENANCE

Decision Traces

Every component choice records reason, evidence, datasheet citation, and confidence. The trace itself becomes the audit log and the training corpus for future Coppr models.

Model Strategy

Own the model. Own the moat.

Frontier models get us to v0 fast. But long-term, Coppr's edge comes from a fine-tuned hardware model trained on a corpus no one else has — every verified design, every reviewed decision, every successful fabrication.

PHASE 01 · 2026

Frontier-powered.

Frontier Claude / GPT-class models drive the agent loop
All structured: tool-calling, IR edits, verification feedback
Datasheet RAG + module memory layered on top
Every design generates structured training data

Fastest path to working product. Pays the bills for what comes next.

PHASE 02 · 2027+

Open-weights, fine-tuned.

Base: Kimi K2, DeepSeek, or Qwen 3 class models
Fine-tuned on Coppr's verified design corpus
No dependency on a frontier lab's training cycles
Specialized models per task: IR generation, layout, BOM, review

The model becomes a moat. The data is ours. The weights are ours.

The Module Library

The moat is encoded engineering.

usb_c_power_input.coppr.yaml

module: usb_c_power_input
parameters:
  mode: sink_5v
  max_current: 3A
  assembly: jlcpcb

provides:
  - net: VBUS  (5V, 3A)
  - net: GND

roles:
  connector:
    type: usb_c_receptacle
    current_min: 3A
  cc1_resistor:
    value: 5.1k  # USB-PD sink
  cc2_resistor:
    value: 5.1k
  esd_protection:
    type: tvs_array

checks:
  - cc_pull_down_required
  - vbus_trace_width >= 0.6mm
  - esd_within_5mm_of_connector
  - jlcpcb_assembly_available

Not just a circuit fragment.

Each module is a parameterized recipe: roles, candidate components, datasheet evidence, layout constraints, and verification checks — all versioned.

Roles over hardcoded parts.

A module declares what it needs (a 3A USB-C receptacle, JLCPCB-assemblable). The agent picks the actual part from a ranked candidate pool with full reasoning.

The library compounds.

Every verified design adds new modules and new candidate parts. Every approved revision becomes training data. The library gets sharper with every board.

This is the moat.

Anyone can fine-tune a model. Few can encode decades of EE judgment into reusable, verifiable, machine-readable form. That is the asset.